Please use this identifier to cite or link to this item: http://prr.hec.gov.pk/jspui/handle/123456789/20846
Title: FPGA Implementation of 3D Shape Recovery Algorithms
Authors: Begum, Farida
Keywords: Engineering & Technology
Electronic Engineering
Issue Date: 2016
Publisher: Mehran University of Engineering & Tech., Jamshoro.
Abstract: The task of retrieving depth/shape information from one or more 2D images is an active research topic within the broad area of Computer Vision. This research proposes a novel Field Programmable Gate Array (FPGA) implementation of 3D shape recovery algorithm using Model Based Design methodology. The 3D shape recovery algorithm presented in this dissertation for hardware implementation is a passive Shape From Focus (SFF) method and is based on work done by Nayar and Nakagawa. Model Based Design approach utilizes a system model as an executable specification throughout design development process. This design technique not only accelerates product development cycle but also offers choice of optimal design alternatives and trade-offs, thus enabling to meet predefined performance criteria. The design methodology is faster and provides a great degree of confidence compared to the manual coding which is tedious, error prone and time consuming. The proposed design methodology is successfully applied to the 3D shape recovery algorithm and whole architecture is implemented on a Xilinx Genesys Virtex5 prototyping board. The automatic generated code in VHDL from Model Based Design which uses MATLAB R2014a for shape recovery algorithm is synthesized with Xilinx ISE Design Suite 14.2 for implementation on FPGA technology. The fixed point optimization of the VHDL model is done which eventually improves FPGA implementation speed suitable for real time simulation. HDL Co-simulation is performed using Mentor Graphic MoelSim 10.3d software to verify the design functionality. Simulation results suggest that the VHDL provided depth estimates is comparable in accuracy to the full precision MATLAB’s output. xv The implemented design on Virtex5 FPGA can work at an estimated frequency of 147.444 MHz and utilizes less than fourth of available hardware resources to produce dense depth map and focused image of a simulated cone object for image sizes up to 200 × 200. So there is possibility of implementing some more parallel processes with this architecture on the same FPGA. In addition, speed, area and power optimization of design is also performed to compare the performance of the designed model. Besides this, FPGA based real time simulation is performed to test and validate the design on actual FPGA hardware. We demonstrate that the modeling and RTL generation time of 3D shape recovery algorithm is reduced by adopting Model Based Design and simulations are accelerated by HDL Verifier along with FPGA-in-loop Co-simulation. Moreover, the generated RTL code can be easily mapped into FPGA, which allows the rapid prototyping of design. Keywords: 3D shape recovery, Shape From Focus, FPGA, Model Based Design, Simulink HDL Coder, HDL Co-simulation, FPGA-in-loop.
Gov't Doc #: 21855
URI: http://prr.hec.gov.pk/jspui/handle/123456789/20846
Appears in Collections:PhD Thesis of All Public / Private Sector Universities / DAIs.

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