Please use this identifier to cite or link to this item: http://prr.hec.gov.pk/jspui/handle/123456789/1663
Title: Hard dware Based B White Box V Verifica ation Met thodolo ogy for r IC Ch hips
Authors: Baig g, Muhammad Iram
Keywords: Applied Sciences
Engineering & allied operations
Other branches of engineering
Electrical engineering
Issue Date: 2010
Publisher: University of Engineering and Technology, Taxila, Pakistan
Abstract: This thesis presents a hardware based testing methodology for speeding up process of verification. With advent of VLSI technology the gate densities on a chip are increasing with rate predicted by Moor’s law. The designers are now mapping complex applications in silicon for enhanced performance and reduced cost. The testing of these designs is becoming more and more challenging. The simulation based testing is very slow and for moderately complex designs takes hours and even days to give decent coverage. The thesis presents novel methodology to test the design by inserting test logic in Hardware. The methodology best works for FPGA based verification. The design is first mapped on FPGA for functional verification. The thesis presents modules that are integrated with the DUTs and monitors the results for correctness. The model also provides white box testing whereby internal working of the design is exploited for exact location of a bug. The methodology also provides assertions based testing and provides coverage analysis of design for a set of test vectors. The thesis gives different examples of circuits that are tested using the proposed methodology. In-silicon White box verification with checkers and monitors holds a great potential in keeping pace with the rapid growth in VLSI technology. The basic idea of our proposed methodology can be termed as a hardware (tester circuitry) testing another hardware (Design under Test). The concept of an embedded layer of re-configurable/removable testing circuit or agent within the hardware of the DUT is proposed and experimented. Starting from simple combinational and sequential circuits to RISC processor and Medium Access Control (MAC) layer found in the IEEE 802.11e standard are tested through this methodology. Two main advantages have been observed: 1) The proposed methodology is found well suited for finding the root causes of the errors in the design under real time. 2) A considerable time saving is observed. The design which takes days in testing with simulation runs, gives equivalent results in minutes when it is run on FPGA prototype along with embedded test agent proposed in this thesis. When device is fully tested and ready for fabrication, this additional tester circuitry can be removed.
URI:  http://prr.hec.gov.pk/jspui/handle/123456789//1663
Appears in Collections:PhD Thesis of All Public / Private Sector Universities / DAIs.

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893S.pdfComplete Thesis2.55 MBAdobe PDFView/Open
893S-0.pdfTable of Contents59.67 kBAdobe PDFView/Open


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