Please use this identifier to cite or link to this item: http://prr.hec.gov.pk/jspui/handle/123456789/6614
Title: Logic Decomposition with Technolgy Mapping for Area and Delay Minimization in FPGA Design
Authors: Dayo, Khalil-ur-rehman
Keywords: Natural Sciences
Physics
Electricity & electronics
Telecommunication engineering
Issue Date: 2006
Publisher: Meharan University of Engineering & Technology, Jamshoro
Abstract: N/A
URI:  http://prr.hec.gov.pk/jspui/handle/123456789//6614
Appears in Collections:PhD Thesis of All Public / Private Sector Universities / DAIs.

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